1. Field of the Invention
The present invention relates to a high voltage generator of the DAC-controlled type.
The invention particularly, but not exclusively, relates to a high voltage generator to be used in a non-volatile memory device and the following description is made with reference to this field of application for convenience of explanation only.
2. Description of the Related Art
As it is well known, different high voltage generators are used in the non-volatile integrated memory devices, for instance Flash NOR memory devices.
Such generators provide voltage signals having a level which lies outside a supply voltage range, normally ranking from a first voltage or power supply voltage Vdd and a second voltage or ground GND.
In essence, a high voltage generator for non-volatile memory devices is a generator of a supply voltage outside the Gnd . . . Vdd range, the generation of such supply voltage being obtained by means of a charge pump circuit or by means of an external supply reference and being regulated by means of a resistive voltage partition compared to a low voltage reference, as it will be explained in the following description.
A high voltage generator of a known type is very schematically shown in FIG. 1, globally indicated with 1. It substantially comprises a voltage control circuit 3 connected to a charge pump circuit 2, which provides at an output terminal OUT a high output voltage Vout, as desired.
The voltage control circuit 3 has an input terminal IN receiving a reference voltage VBG as well as first and second output terminals connected to respective first and second input terminals, I1 and I2, of the charge pump circuit 2.
More particularly, the voltage control circuit 3 comprises an operational amplifier 4 having a first input terminal, in particular a non-inverting one (+), connected to the input terminal IN, a second input terminal, in particular an inverting one (−) and an output terminal O1 connected, by means of an inverting buffer 5, to the first input terminal I1 of the charge pump circuit 2 as well as to an oscillator 6, having in turn an output terminal connected to the second input terminal I2 of the charge pump circuit 2 and providing thereto a frequency modulated signal f_mod. The inverting buffer 5 further provides a command signal STOP/GO to the first input terminal I1 of the charge pump circuit 2.
The reference voltage VBG currently used is a well known band-gap voltage and it is to be compared to a partition Vout*rho of the output voltage Vout. In this aim, the high voltage generator 1 further comprises a resistor divider 7 which is inserted between the output terminal OUT and ground GND and has a central node XP connected to the inverting input terminal (−) of the operational amplifier 4 which provides thereto a partition voltage Vpart.
Moreover, the resistor divider 7 comprises a first Rup and a second resistor Rdwn, connected, in series to each other, between the output terminal OUT and ground GND.
These resistors are sized in such a way that the following relation is verified:Rdwn/(Rup+Rdwn)=rho
In this way, the high voltage generator 1 of FIG. 1 shows the following advantageous features:                low current absorption from the output terminal OUT. In this aim, a high value for the total resistance of the resistor divider 7 (equal to Rup+Rdwn) is suitably chosen so that a small amount of current is drawn by the output terminal OUT; and        low dependence on the process drift. In particular, the resistors Rup and Rdwn of the resistor divider 7 can have a stable partition ratio rho which is independent from the process drift and from the material physically realizing such resistors. Moreover, in this aim, a very high value can be chosen for the gain of the operational amplifier 4.        
It is thus clear that the high voltage generator 1 provides an output voltage Vout having a voltage level which is approximately equal to VBG/rho and depends on an external load connected to the output terminal OUT, on the output resistance value of the charge pump circuit 2 and on the regulation accuracy.
In particular, the regulation obtained thanks to the voltage control circuit 3 can be:                a digital one, by switching ON/OFF the charge pump circuit 2 on the basis of the command signal STOP/GO having a first value STOP and a second value GO corresponding to the conditions Vout>VBG/rho and Vout<VBG/rho, respectively, in turn corresponding to a switching off, respectively on, of the charge pump circuit 2; and        an analog one, by modulating a working frequency of the charge pump circuit 2 on the basis of the frequency modulated signal f_mod provided by the oscillator 6.        
Moreover, the high voltage generator 1 shown in FIG. 1 is of the DAC controlled type and further comprises a low voltage digital-to-analog converter or LV DAC 8 providing on a second bus 9B a regulation signal REG to the resistor divider 7.
The LV DAC 8 operates by a direct or virtual modulation of the partition of the output voltage Vout provided by the resistor divider 7, the partition value depending on an input digital signal, as will be explained in the following description.
More particularly, the LV DAC 8 has an input terminal ID connected to a control bus 9 and receiving therefrom a digital control signal N_Bin of k bit as well as an output terminal OD connected by the second bus 9B to the resistor divider 7, in particular to a modulable resistor Rdwn comprised therein, and providing thereto the regulation signal REG.
In this way, the resistance value of resistor divider 7 depends on the regulation signal REG and thus from the digital control signal N_Bin on the control bus 9, usually comprising a plurality of control values (in the example shown in the figure, 2k values) which are established by a digital controller, for instance a microprocessor, not shown in the figure, connected to the control bus 9.
The LV DAC regulator 8 and the resistor divider 7 thus form an output regulator 8A connected to the output terminal OUT of the high voltage generator 1.
In essence, the high voltage generator 1 as a whole works as a DAC.
It should be remarked that a high voltage generator 1 can be also realized in a simple manner by connecting an operational amplifier to an appropriate external high voltage line, as schematically shown in FIG. 2.
To structurally and/or functionally equal elements with respect to the high voltage generator described with reference to FIG. 1, same reference numbers will be applied.
In particular, according to this modified embodiment, the voltage control circuit 3 comprises an operational amplifier 4 and the charge pump circuit 2 is substituted by a cascode transistor MOUT, for instance a MOS transistor of the N type, inserted between an external high voltage line Vpp and an output terminal OUT of the high voltage generator 1. The operational amplifier 4 is also connected to the external high voltage line Vpp and has an output terminal O1 connected to a control or gate terminal G of the cascode transistor MOUT.
As previously, the high voltage generator 1 further comprises a resistor divider 7 which is inserted between the output terminal OUT and ground GND and has a central node XP connected to the inverting input terminal (−) of the operational amplifier 4 which provides thereto a partition voltage Vpart.
Moreover, the resistor divider 7 comprises a first Rup and a second resistor Rdwn, connected, in series to each other, between the output terminal OUT and ground GND.
The high voltage generator 1 further comprises a low voltage digital-to-analog converter or LV DAC 8 having an input terminal ID connected to a control bus 9 and receiving therefrom a digital control signal N_Bin of k bit as well as an output terminal OD connected by a second bus 9B to the resistor divider 7, in particular to a modulable resistor Rdwn comprised therein, and providing thereto a regulation signal REG.
The LV DAC regulator 8 and the resistor divider 7 thus form an output regulator 8A connected to the output terminal OUT of the high voltage generator 1.
The high voltage generator 1 of FIG. 2 provides for an analog regulation thanks to the operational amplifier 4 which is supplied with an external high voltage, also indicate with Vpp for sake of simplicity, and drives the gate terminal G of the cascode transistor MOUT.
In any case, a DAC-controlled high voltage generator works in a voltage range—from a bottom level to a top level—being defined as follows:                the top level is a maximum voltage value for which the charge pump circuit 2 (or the cascode transistor MOUT, as driven by the voltage control circuit 3) can be considered as a voltage generator which is independent of the load applied thereto; and        the bottom level is tied to the condition wherein the voltage control circuit 3 is able to correctly compare the output voltage Vout and the band gap input voltage VBG.        
For the scheme shown in FIG. 1, the voltage control circuit 3 cannot correctly work when Vout<VBG, being always rho<1 in a voltage divider.
The limitation of the bottom level is however not satisfactory when the high voltage generator 1 is used in non-volatile memory devices, in particular of the Flash NOR type, of new generation.
It is in fact known that new generation memory devices are realized according to technologies characterized by linear sizes and thicknesses more and more reduced as well as really low driving voltages.
In particular, the modify operations, i.e. the cell writing and erasing operations, are performed by using staircase voltages which should start as low as possible, substantially at a first level which is equal or even lower than the band gap input voltage VBG.
In the field of the non-volatile memory devices, the DAC-controlled high voltage generator is thus usually modified as shown in FIG. 3, globally and schematically indicated with 10. In particular, such high voltage generator 10 is used to provide—as output voltage Vout—a program voltage (usually labelled Vxp) for non-volatile memory cells.
To structurally and/or functionally equal elements with respect to the high voltage generators described with reference to FIGS. 1 and 2, same reference numbers will be applied.
The high voltage generator 10 thus comprises a charge pump circuit 2 having an input terminal I1 connected to a voltage control circuit 3 and an output terminal connected to the output terminal OUT of the high voltage generator 10.
The voltage control circuit 3 comprises an operational amplifier 4 having a first non-inverting input terminal (+) and a second inverting input terminal (−) as well as an output terminal O1 connected to an inverting buffer 5, which has in turn an output terminal X connected to the input terminal I1 of the charge pump circuit 2 and providing thereto a command signal STOP/GO.
The high voltage generator 10 also comprises a LV DAC regulator 8 having an input terminal ID connected to a control bus 9 and receiving therefrom a digital control signal N_Bin of k bit as well as an output terminal OD connected to the operational amplifier 4, in particular to the non inverting input terminal (+) and providing thereto a converted control voltage Vconv_LV, which is an analog conversion of the digital control signal N_Bin.
The high voltage generator 10 further comprises a measuring circuit or MEAS circuit 11A having an input terminal IM connected to the output terminal OUT and receiving therefrom the output voltage Vout as well as an output terminal OM connected to the inverting input terminal (−) of the operational amplifier 4 and providing thereto a measured voltage Vmeas.
Essentially, the MEAS circuit 11A detects the output voltage Vout and provides the measured voltage Vmeas which is substantially such output voltage Vout suitably reduced in order to lie within the supply range GND . . . Vdd.
In this way, the operational amplifier 4 provides for a comparison between the converted control voltage Vconv_LV and the measured voltage Vmeas in order to decide whether the charge pump circuit 2 has to be switched on or off.
The LV DAC regulator 8 and the MEAS circuit 11A thus form an output regulator 8B connected to the output terminal OUT of the high voltage generator 1.
The high voltage generator 10 also comprises a discharge circuit 12 inserted between the voltage control circuit 3 and the output terminal OUT and comprising a logic gate 13 having a first input terminal connected to the voltage control circuit 3, namely to the output terminal X of the inverting buffer 5, a second input terminal IS receiving an enabling signal Up_Down and an output terminal connected to a control or gate terminal of a discharge transistor Mds, in turn inserted between the output terminal OUT and ground GND.
The discharge circuit 12 is enabled when the output voltage Vout has a voltage value which is higher than a desired one and provides for the discharging of the output terminal OUT.
It should be noted that such a discharge circuit 12 is needed only in case of a capacitive load applied to the output terminal OUT (or in case of a load comprising a resistive element which is not connected to ground GND). In this case the enabling signal Up_Down, provided by an external control circuit, is usually enabled when the voltage required by the DAC (i.e. the digital value of the signal N_Bin) commutes to a lower value.
In the following description, the charge pump circuit is considered as comprising a discharge circuit, if needed, the discharge circuit being activated when the charge pump circuit is off.
More particularly, as shown in FIG. 4A, the LV DAC regulator 8 comprises a multiple current generator 14 having an input terminal connected to the input terminal ID of the LV DAC regulator 8 and thus to the control bus 9, receiving therefrom the digital control signal N_Bin and an output terminal connected to the output terminal OD of the LV DAC regulator 8, as well as to a current/voltage converter 15, which has a resistance value Rout.
In this way, an output current Ird*N provided by the multiple current generator 14 on the basis of the digital control signal N_Bin is converted by the current/voltage converter 15 into the control voltage Vconv_LV and provided to the output terminal OD of the LV DAC regulator 8.
The multiple current generator 14 is also connected to a reference current/voltage generator 16, in turn connected to a band gap terminal BGr and receiving therefrom a band gap voltage VBG. The reference current/voltage generator 16 provides a reference voltage Viref_DAC to the reference input terminal IDR of the LV DAC regulator 8.
More particularly, as it will be clear in the following description, the reference current/voltage generator 16 generates a reference current Ird and associates thereto the reference voltage Viref_DAC, which is then used by the multiple current generator 14 in order to generate a current which a multiple or a submultiple of this reference current Ird by a factor N [which is an integer number associated to the digital control signal N_Bin]. Moreover, the final obtained current is then used to generate the converted control voltage Vconv_LV by the resistance value Rout of the current/voltage converter 15.
A possible circuital implementation of the reference voltage generator 16 and of the multiple current generator 14 is shown in greater detail in FIG. 4B.
The reference current/voltage generator 16 comprises an operational amplifier 17 having a first inverting input terminal (−) connected to the band gap terminal BGr, a second non-inverting input terminal (+) connected to an internal node Xbg as well as an output terminal connected to the reference input terminal IDR of the multiple current generator 14.
The reference current/voltage generator 16 further comprises a pull-down or evaluation resistor Rdwn, inserted between the internal node Xbg and ground GND, as well as a pull-up transistor Mup, inserted between the voltage supply Vdd and the internal node Xbg and having a control or gate terminal connected to the output terminal of the operational amplifier 17 and thus to the reference input terminal IDR of the multiple current generator 14.
It should be noted that the non-inverting input terminal (+) of the operational amplifier 17 provides to the internal node Xbg a voltage BG_copy_R which is a copy of the band gap voltage VBG, a reference current Ird flowing from the pull-up transistor Mup being thus equal to:Ird=VBG/Rdwn
Moreover, the multiple current generator 14 comprises a plurality of pull-up/pull-down transistor pairs, inserted between the reference input terminal IDR and the output terminal OD of the LV DAC regulator 8, these transistor pairs being as many as the digital size K of the digital control signal N_Bin is.
In particular, each transistor pair comprises a pull-up transistor Mupi and a pull-down transistor Mdwi (being i=0 . . . k), inserted, in series to each other, between the supply voltage reference Vdd and the output terminal OD, the pull-up transistor Mupi having a control or gate terminal connected in a mirror configuration to the supply voltage reference Vdd while the pull-down transistor Mdwi has its control or gate terminal IDi connected to the control bus 9 and receiving therefrom a corresponding digital control value N_Bin_i.
In essence, the multiple current generator 14 comprises a plurality of current mirrors to provide at the output terminal OD (which is connected to the current/voltage converter 15, as previously explained) a final output current Ird*N depending on the digital control signal N_Bin on the control bus 9, thus obtaining the converted control voltage Vconv_LV.
A circuital implementation of the MEAS circuit 11A is schematically shown in FIG. 4C.
More particularly, the MEAS circuit 11A comprises an operational amplifier 18 having its first non-inverting input terminal (+) connected to a Band Gap terminal BGm and receiving therefrom a Band Gap voltage VBG (this Band Gap terminal BGm being the input terminal IN of the high voltage generator 10), a second inverting input terminal (−) connected to an internal node XbgM and an output terminal connected to a control or gate terminal of a measuring transistor Mmeas, being in turn inserted between the internal node XbgM and the output terminal OM of the MEAS circuit 11A. It should be noted that the inverting input terminal (−) of the operational amplifier 18 provides to the internal node XbgM a voltage BG_copy_M which is a copy of the band gap voltage VBG, generated in a dual manner with respect to the voltage BG_copy_R provided to the internal node Xbg of the reference current/voltage generator 16 connected to the LV DAC regulator 8.
The MEAS circuit 11A further comprises a pull-up or measuring resistor Rup inserted between its input terminal IM and the internal node XbgM, a measuring current Imeas flowing through the measuring resistor Rup and the measuring transistor Mmeas, being in series to each other.
Finally, the MEAS circuit 11A comprises a current/voltage converter 19, inserted between the output terminal OM and ground GND and providing to this output terminal OM the measured voltage Vmeas.
In summary, the signals provided by the DAC regulator 8 and by the MEAS circuit 11 are generated according to the following formula:Vconv—LV=N*VBG*Rout/Rdwn
being N an integer number associated to the digital control signal N_Bin of the control bus 9, Rout the resistance of the current/voltage converter 19, (which must match as better as possible the Rout of the I/V converter 15 in the DAC 8) and Rdwn is the resistance value of the evaluation resistor.Vmeas=(Vout−VBG)*Rout/Rup
being Rup a resistance value of the measuring resistor.
It is thus clear that the switching of the operational amplifier 4 corresponds to the following condition:Vconv—LV=Vmeas→Vout=VBG*(1+k*Rup/Rdwn)
In other words, the high voltage generator 10 shown in FIG. 3 provides for a regulation of the evaluation resistor Rdwn based on a fraction of its resistance value, according to the integer number N associated to the digital control signal N_Bin.
Also in this case, the regulation becomes difficult when the output voltage Vout reaches the band gap voltage VBG and cannot be realized when Vout<VBG, not overcoming the above described problem.
Also known are high voltage generators comprising a main DAC regulator in parallel to other regulators, each of which is dedicated to an extra regulation value and being activated according to the value of additional bits of the digital control signal N_Bin on the control bus 9.
This approach leads to a rather complex architecture that cannot be considered as a true DAC-controlled high voltage generator extended below the VBG voltage.